Design Full Adder Using 8 1 Mux

Full Adder

Combinational logic circuits

John Crowe , Barrie Hayes-Gill , in Introduction to Digital Electronics, 1998

4.1.5 Full adders

A full adder circuit is central to most digital circuits that perform addition or subtraction. It is so called because it adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit. ¹ It therefore has three inputs and two outputs. The truth table and corresponding Karnaugh maps for it are shown in Table 4.6.

Table 4.6. The truth table and Karnaugh maps for a full adder. X and Y are the two bits to be added, C _in and C _out the carry-in and carry-out bits, and S the sum

Example 4.9

Two 1's with no carry-in are added using a full adder. What are the outputs?

Solution

Adding two 1's in binary gives a result of 0 with a carry-out of 1. So S=0 and C _out = 1. (In decimal this is saying 1 +1=2, in binary 01+01 = 10.)

Example 4.10

Two 1's with a carry-in of 1 are added using a full adder. What are the outputs?

Solution

Here the result is 1 carry 1, that is S= 1 and C _out= 1. (In decimal 1 + 1 + 1 (carry-in) = 3; in binary 01+01 + 1 (carry-in) = 11.)

Using the Karnaugh maps to obtain minimised expressions for S and C _out, we notice the chequerboard pattern of an XOR gate in the sum term to give:

$S=X\oplus Y\oplus C_{\text{in}}$

whilst

$C_{\text{out}}=XY+X{C}_{\text{in}}+Y{C}_{\text{in}}$

The circuit to implement the full adder is shown in Fig. 4.13.

Fig. 4.13. Circuit diagram of a full adder

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Introduction to Digital Logic Design

Ian Grout , in Digital Systems Design with FPGAs and CPLDs, 2008

Example 3: One-Bit Full-Adder

The full-adder extends the concept of the half-adder by providing an additional carry-in (Cin) input, as shown in Figure 5.21. This is a design with three inputs (A, B, and Cin) and two outputs (Sum and Cout). This cell adds the three binary input numbers to produce sum and carry-out terms.

Figure 5.21. One-bit full-adder cell

The truth table for this design is shown in Table 5.26.

Table 5.26. One-bit full-adder cell truth table

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

From viewing the truth table, the Sum output is only a logic 1 when one or three (but not two) of the inputs is logic 1. The Boolean expression for this is (in reduced form):

$\text{Sum}=\text{Cin}\oplus (\text{A}\oplus \text{B})$

From viewing the truth table, the Cout output is only a logic 1 when two or three of the inputs is logic 1. The Boolean expression for this is (in reduced form):

$\text{Cout}=(\text{A}\text{.B})+(\text{Cin}\text{.}(\text{A}\oplus \text{B}))$

This can be drawn as a circuit schematic as shown in Figure 5.22.

Figure 5.22. One-bit full-adder circuit schematic

Any number of half- and full-adder cells can be connected together to form an n-bit addition. Figure 5.23 shows the connections for a four-bit binary adder. In this design, there is no Cin input. Inputs A and B are four bits wide, and bit 0 (A(0) and B(0)) are the LSBs.

Figure 5.23. Four-bit binary adder

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Two-Operand Addition

Miloš D. Ercegovac , Tomás Lang , in Digital Arithmetic, 2004

Carry-Ripple Adder

2.1

In the full-adder implementation with two half-adders, the load on the carry-in is larger than the load on other signals. Since the delay of the carry-out signal is affected by this load, it is convenient to reduce it. One possibility is to include an inverter in the carry-in input to the XOR gate producing s_i and to change the XOR to an XNOR. Determine the effect of this modification on the delay of the carry-out signal, using the characteristics of Table 2.4 (average delay).

TABLE 2.4. Characteristics of a family of CMOS gates.

		Propagation Delays
Gate Type	Fanin	tp LH(ns)	tpHL(ns)	tp (average)(ns)	Load Factor (standard loads)	Size (equivalent gates)
AND	2	0.15 +0.037 L	0.16+0.017 L	0.16+ 0.027 L	1.0	2
AND	3	0.20+0.038 L	0.18+0.018 L	0.19+ 0.028 L	1.0	2
AND	4	0.28+0.039 L	0.21+0.019 L	0.25+ 0.029 L	1.0	3
AND	2	0.15 +0.037 L	0.16+0.017L	0.16+ 0.027 L	1.0	2
AND	3	0.20+0.038 L	0.18+0.018 L	0.19+ 0.028 L	1.0	2
AND	4	0.28+0.039 L	0.21+0.019 L	0.25+ 0.029 L	1.0	3
AND	2	0.15 +0.037 L	0.16+0.017L	0.16+ 0.027 L	1.0	1
AND	3	0.20+0.038 L	0.18+0.018 L	0.19+ 0.028 L	1.0	1
AND	4	0.28+0.039 L	0.21+0.019 L	0.25+ 0.029 L	1.0	2
OR	2	0.12+0.037 L	0.20+0.019 L	0.16+ 0.028 L	1.0	2
OR	3	0.12+0.038 L	0.34+0.022 L	0.23+ 0.025 L	1.0	4
OR	4	0.13 +0.038 L	0.45+0.025 L	0.29+ 0.032 L	1.0	5
NOT	1	0.02+0.038 L	0.05+0.017 L	0.04+ 0.028 L	1.0	6
NAND	2	0.05+0.038 L	0.08+0.027 L	0.07+ 0.033 L	1.0	1
NAND	3	0.07+0.038 L	0.09+0.039 L	0.08+ 0.039 L	1.0	2
NAND	4	0.10+0.037 L	0.12+0.051 L	0.11+0.045 L	1.0	4
NAND	5	0.21+0.038 L	0.34+0.019 L	0.28+0.029 L	1.0	4
NAND	6	0.24+0.037 L	0.36+0.019 L	0.30+0.028 L	1.0	5
NAND	8	0.24+0.038 L	0.42 +0.019 L	0.33+0.029 L	1.0	6
NOR	2	0.06+0.075 L	0.07+0.016 L	0.07+0.046 L	1.0	1
NOR	3	0.16+0.111 L	0.08+0.017 L	0.12+0.059 L	1.0	2
NOR	4	0.23+0.149 L	0.08+0.017 L	0.16+0.083 L	1.0	4
NOR	5	0.38+0.038 L	0.23 +0.018 L	0.32+0.028 L	1.0	4
NOR	6	0.46+0.037 L	0.24+0.018 L	0.35+0.028 L	1.0	5
NOR	8	0.54+0.038 L	0.23+0.018 L	0.39+0.028 L	1.0	6
XOR +	2*	0.30+0.036 L	0.30+0.021 L	0.30+0.029 L	1.1	3
		0.16+0.036 L	0.15+0.020 L	0.15+0.028 L	2.0
XOR +	3*	0.50+0.038 L	0.49+0.027 L	0.50+0.033 L	1.1	6
		0.28+0.039 L	0.27+0.027 L	0.28+0.033 L	2.4
		0.19+0.036 L	0.17+0.025 L	0.18+0.032 L	2.1
2-OR/NAND 2	4	0.17+0.075 L	0.10+0.028 L	0.14+0.052 L	1.0	2
2-AND/NOR 2	4	0.17+0.075 L	0.10+0.028 L	0.14+0.052 L	1.0	2
2-MUX	2	0.20+0.050 L	0.22+0.050 L	0.21+0.050 L	0.5	2

L

load on the gate output

*

different characteristics for each input

+

XNOR same characteristics as XOR; for full-adder characteristics see Table 2.2

2.2

Determine the delay of a 32-bit adder using the full-adder characteristics of Table 2.4 (average delays).

2.3

Design a radix-4 full adder using the CMOS family of gates shown in Table 2.4. Compare delay and size with a 2-bit carry-ripple adder implemented with (radix-2) full-adders (use average delays).

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Multioperand Addition

Miloš D. Ercegovac , Tomás Lang , in Digital Arithmetic, 2004

Example 3.2

The reduction by columns for m = 8 magnitudes of n = 5 bits is shown in Table 3.4

TABLE 3.4. Example of reduction process.

	i
	6	5	4	3	2	1	0
l=4
ei			8	8	8	8	8
m 3			6	6	6	6	6
hi			0	0	0	1	0
fi			2	2	2	1	1
l=3
ei		2	6	6	6	6	6
m 2		4	4	4	4	4	4
hi		0	0	0	0	1	0
fi		0	2	2	2	1	1
l=2
ei		4	4	4	4	4	4
m1		3	3	3	3	3	3
hi		0	0	0	0	0	1
fi		1	1	1	1	1	0
l=1
ei	1	3	3	3	3	3	3
m0	2	2	2	2	2	2	2
hi	0	0	0	0	0	0	1
fi	0	1	1	1	1	1	0

The resulting array of full-adders and half-adders is shown in Figure 3.21 It has 26 full-adders and 4 half-adders. For the final 2-to-l reduction, a 7-bit CPA is needed.

FIGURE 3.21. Reduction by columns of eight 5-bit magnitudes. Cost of reduction: 26 FAs and 4 HAs.

The delay in the critical path is roughly

3.38 $\begin{array}{l}T=t_{csa.tree}+t_{\mathcal{C}PA}\\ =4t_{fa}+t_{CPA(7)}\end{array}$

The total delay of the scheme consists of the delay of the reduction array and the delay of the final CPA. Since the delay of the CPA depends on the number of bits, a more aggressive reduction might be applied to reduce the precision of the final adder at the expense of additional counters (Exercise 3.22).

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Arithmetic circuits

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. WOODS MA, DPhil , in Digital Logic Design (Fourth Edition), 2002

12.10 Serial addition and subtraction

For parallel addition a full adder is required for each stage of the addition and carry ripple can be eliminated if carry look-ahead facilities are available. An alternative approach is to use a serial addition technique which requires a single full adder circuit and a small amount of additional logic for saving the carry. Serial addition takes longer, but a smaller quantity of hardware is required and the selection of serial or parallel addition depends upon the trade-off between speed and cost.

A serial adder uses a sequential technique and may be regarded as a very simple finite state machine. The basic element of the circuit is a full adder which is operated in conjunction with a DFF and a pair of shift registers which have parallel loading and shift right facilities controlled by Ck1 and Ck2. The selection of either of the two clock pulses is a function of the mode control M (see Figure 12.12). With M = 0, Ck2 is enabled, the flip-flop is cleared, and the registers are loaded with the two numbers to be added so that the two least significant bits are available at terminals A and B. The corresponding sum and carry-out appear at the output terminals of the full adder. With M = 1, Ck2 is disabled and Ck1 is enabled. Ck1 is now used to shift right the digits in registers R ₁ and R ₂, thus presenting the next most significant pair of digits at terminals A and B. Additionally C _o is clocked to the output of the flip-flop and becomes the next C _in, while the sum of the two least significant digits is clocked into the left-hand end of R ₁ This process is repeated on receipt of each clock pulse (Ck1) until the two numbers stored initially in R ₁ and R ₂ have been added and the resulting sum has been clocked back into the register R ₁ If at the termination of the addition C _o = 1, this will represent the most significant digit of the sum.

Figure 12.12. A serial addition circuit

The serial adder can also be used in the subtraction mode, as shown in Figure 12.13. The B digits are inverted when the mode signal M = 1 but an initialisation pulse I of short time duration is required at the input of g₁ at the same time that the least significant pair of digits appear at the full adder inputs. The initialisation pulse is used to preset the DFF to 1, thus forming the 2's complement of the number entering sequentially at the B input. A similar arrangement is made when the adder is in the addition mode. The mode signal M = 0 and a short initialisation pulse is needed at the input of g₂ to clear the DFF so that C _in = 0.

Figure 12.13. Serial adder/subtracter

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Digital Building Blocks

Sarah L. Harris , David Harris , in Digital Design and Computer Architecture, 2022

Putting It All Together

This section introduced the half adder, full adder, and three types of carry propagate adders: ripple-carry, carry-lookahead, and prefix adders. Faster adders require more hardware and therefore are more expensive and power-hungry. These trade-offs must be considered when choosing an appropriate adder for a design.

Hardware description languages provide the + operation to specify a CPA. Modern synthesis tools select among many possible implementations, choosing the cheapest (smallest) design that meets the speed requirements. This greatly simplifies the designer's job. HDL Example 5.1 describes a CPA with carries in and out, and Figure 5.8 shows the resulting hardware.

HDL Example 5.1

Carry Propagate Adder (CPA)

SystemVerilog

module adder #(parameter N = 8)

  (input   logic [N–1:0] a, b,

  input   logic   cin,

  output logic [N–1:0] s,

  output logic   cout);

  assign {cout, s} = a + b + cin;

endmodule

VHDL

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD_UNSIGNED.ALL;

entity adder is

  generic(N: integer := 8);

  port(a, b: in   STD_LOGIC_VECTOR(N–1 downto 0);

  cin:   in   STD_LOGIC;

  s:   out STD_LOGIC_VECTOR(N–1 downto 0);

  cout: out STD_LOGIC);

end;

architecture synth of adder is

  signal result: STD_LOGIC_VECTOR(N downto 0);

begin

  result <= ("0" & a) + ("0" & b) + cin;

  s   <= result(N–1 downto 0);

  cout   <= result(N);

end;

Figure 5.8. Synthesized adder

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DSP Integrated Circuits

Lars Wanhammar , in DSP Integrated Circuits, 1999

Data-Flow Description

The data-flow description is typically used to describe the system as the flow of data between different units—for example, memories and processing elements. Timing properties are taken into account by describing signal waveforms. Functions to be performed are isolated in block declarations. The activation of blocks is controlled by guarded statements. All signal assignments transpire concurrently. The data-flow description is suitable for description and simulation of signal-flow graphs.

We illustrate some of the basic concepts used in VHDL by the code for a full-adder and a test bench that can be used to validate the code.

Example 1.2

Box 1.2 shows the VHDL code that describes a full-adder. The full-adder is realized by using two half-adders and an OR gate.

Box 1.2

VHDL description of a half-adder and a full-adder

-- ENTITY DECLARATIONS

entity Half_Adder is

port(X, Y: in Bit; Sum, Carry: out Bit);

end Half_Adder;

entity OR_gate is

port (In₁, In₂: in Bit; Out₁: out Bit);

end OR_gate;

-- ARCHITECTURAL BODIES

architecture Behavior_desc of Half_Adder is

begin

process

begin

  Sum   <   = X or Y after 5   ns;

  Carry   <   = X and Y after 5   ns;

wait on X, Y;

end process;

end Behavior_desc;

architecture Behavior_desc of OR_gate is

begin

process

begin

  Out₁  <   = In₁ or In₂ after 5   ns;

wait on In₁, In₂;

end process;

end Behavior_desc;

-- ENTITY DECLARATION

entity Full_Adder is

port(A, B, Carry_in: in Bit; Sum, Carry_out: out Bit);

end Full_Adder;

-- ARCHITECTURAL BODY

architecture Structure of HalfAdder is

-- Signal declarations

signal Temp_sum, Temp_carry₁, Temp_carry₂: Bit;

-- Local declarations

component HA

port(X, Y: in Bit; Sum, Carry: out Bit);

end component HA;

component OG

port(In₁, In₂: in Bit; Out₁: out Bit);

end component OG;

for U₀: HA use entity Half_Adder(Behavior_desc);

for U₁: HA use entity Half_Adder(Behavior_desc);

for U₂: OG use entity OR_gate(Behavior_desc);

begin-- Connect the ports of the components

U₀: HA

port(X =   >   A, Y =   >   B, Sum =   >   Temp_sum, Carry =   >   Temp_carry₁);

U₁:HA

port(X =   >   Temp_sum, Y =   >   Carry_in, Sum =   >   Sum, Carry =   >   Temp_carry₂);

U₂: OG

port(In₁ =   >   Temp_carry₁, In₂ =   >   Temp_carry₂, Out₁ =   >   Carry_out);

end Structure;

First we declare the two entities Half_Adder and OR_gate and their architectural bodies in a behavioral style.

Note that there is a special assignment operator used to propagate signals (<=). The statement wait on X, Y; suspends the logic process until at least one of the signals, X or Y, is changed. Next we declare the design entity Full_Adder and its port map. A structural style is used in the architectural body for the full-adder. The description is in terms of the previously defined components.

Example 1.3

Box 1.3 shows the VHDL code for a test bench for testing the full-adder described in Example 1.2.

Box 1.3

VHDL description of a test bench for the full-adder

-- ENTITY DECLARATION

entity Test_gen is

port(A, B, Carry_in: in Bit; Sum, Carry_out: out Bit);

end Test_gen;

-- ARCHITECTURAL BODY

architecture Behavior_desc of Test_gen is

begin

A   &lt;   = ′1′, ′0′ after 20   ns, ′0′ after 40   ns, ′0′ after 60   ns, ′0′ after 80   ns, ′1′ after 100   ns,

  ′1′, after 120   ns, ′1′ after 140   ns, ′1′ after 160   ns, ′0′ after 180   ns;

B   &lt;   = ′1′, ′0′ after 20   ns, ′0′ after 40   ns, ′1′ after 60   ns, ′1′ after 80   ns, ′0′ after 100   ns,

  ′0′, after 120   ns, ′1′ sifter 140   ns, ′1′ after 160   ns, ′0′ after 180   ns;

Carry_in   &lt;   = ′1′, ′0′ after 20   ns, ′1′ after 40   ns, ′0′ after 60   ns, ′1′ after 80   ns,

  ′0′ after 100   ns, ′1′ after 120   ns, ′0′ after 140   ns, ′1′ after 160   ns,

  ′0′ after 180   ns;

end Behavior_desc;

-- Dummy entity for the test bench

entity Test_bench is

end Test_bench;

-- ARCHITECTURAL BODY

architecture Behavior_desc of Test_bench is

signal x, y, z, u, v: Bit;

component Generator

port(A, B, Carry_in: in Bit; Sum, Carry_out: out Bit);

end component;

component Adder

port(A, B, Carry_in: in Bit; Sum, Carry_out: out Bit);

end component;

for S₀: Generator use entity Test_gen(Behavior_desc);

for S₁: Adder use entity Full_Adder(Behavior_desc);

begin --Connect the ports of the components

S₀: Generator

port(x, y, z, u, v);

S₁: Adder

port(x, y, z, u, v);

end Behavior_desc;

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Hardware Description Languages

Sarah L. Harris , David Money Harris , in Digital Design and Computer Architecture, 2016

4.2.5 Internal Variables

Often it is convenient to break a complex function into intermediate steps. For example, a full adder, which will be described in Section 5.2.1, is a circuit with three inputs and two outputs defined by the following equations:

(4.1) $\begin{array}{l}S=A\oplus B\oplus C_{\text{in}}\hfill \\ C_{\text{out}}=AB+A{C}_{\text{in}}+B{C}_{\text{in}}\hfill \end{array}$

If we define intermediate signals, P and G,

(4.2) $\begin{array}{l}P=A\oplus B\hfill \\ G=AB\hfill \end{array}$

we can rewrite the full adder as follows:

(4.3) $\begin{array}{l}S=P\oplus C_{\text{in}}\hfill \\ C_{\text{out}}=G+P{C}_{\text{in}}\hfill \end{array}$

Check this by filling out the truth table to convince yourself it is correct.

P and G are called internal variables, because they are neither inputs nor outputs but are used only internal to the module. They are similar to local variables in programming languages. HDL Example 4.7 shows how they are used in HDLs.

HDL Example 4.7

Full Adder

SystemVerilog

In SystemVerilog, internal signals are usually declared as logic.

module fulladder(input   logic a, b, cin,

  output logic s, cout);

  logic p, g;

  assign p = a ^ b;

  assign g = a &amp; b;

  assign s = p ^ cin;

  assign cout = g | (p &amp; cin);

endmodule

VHDL

In VHDL, signals are used to represent internal variables whose values are defined by concurrent signal assignment statements such as p &lt;= a xor b;

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity fulladder is

  port(a, b, cin: in   STD_LOGIC;

  s, cout:   out STD_LOGIC);

end;

architecture synth of fulladder is

  signal p, g: STD_LOGIC;

begin

  p &lt;= a xor b;

  g &lt;= a and b;

  s &lt;= p xor cin;

  cout &lt;= g or (p and cin);

end;

HDL assignment statements (assign in SystemVerilog and <= in VHDL) take place concurrently. This is different from conventional programming languages such as C or Java, in which statements are evaluated in the order in which they are written. In a conventional language, it is important that S = P ⊕ C _in comes after P = A ⊕ B, because statements are executed sequentially. In an HDL, the order does not matter. Like hardware, HDL assignment statements are evaluated any time the inputs, signals on the right hand side, change their value, regardless of the order in which the assignment statements appear in a module.

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Digital Building Blocks

Sarah L. Harris , David Money Harris , in Digital Design and Computer Architecture, 2016

Ripple-Carry Adder

The simplest way to build an N-bit carry propagate adder is to chain together N full adders. The C _out of one stage acts as the C _in of the next stage, as shown in Figure 5.5 for 32-bit addition. This is called a ripple-carry adder. It is a good application of modularity and regularity: the full adder module is reused many times to form a larger system. The ripple-carry adder has the disadvantage of being slow when N is large. S ₃₁ depends on C ₃₀, which depends on C ₂₉, which depends on C ₂₈, and so forth all the way back to C _in, as shown in blue in Figure 5.5. We say that the carry ripples through the carry chain. The delay of the adder, t _ripple, grows directly with the number of bits, as given in Equation 5.1, where t_FA is the delay of a full adder.

Figure 5.5. 32-bit ripple-carry adder

Schematics typically show signals flowing from left to right. Arithmetic circuits break this rule because the carries flow from right to left (from the least significant column to the most significant column).

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Square Root by Digit Recurrence

Miloš D. Ercegovac , Tomás Lang , in Digital Arithmetic, 2004

Characteristics of the Implementation

6.2

Design a 12-bit radix-2 square root unit at the gate level. You may use full-adders, multiplexers, registers, and gates. Provide the necessary design details to establish delays of critical paths. Use a carry-save adder to form residuals in redundant form. Give an estimate of the overall delay in gate delay units (t_g ) and cost. Assume that a full-adder has a delay of 4t_g , a 3-1 multiplexer 2t_g , and a register load 3t_g .

6.3

Develop the following two ways of generating the adder input F when a signed-digit adder is used:

(a)

Use S[j] in its original signed-digit form.

(b)

Convert S[j] to two's complement representation. Discuss the design trade-offs in these alternatives.

6.4

[Retiming of the recurrence]. As Exercise 5.7, but for square root.

6.5

[Overlapped radix-2 stages]. Consider a radix-2 square root algorithm with the result-digit set {−1, 0, 1} and redundant residuals in carry-save form. The result-digit selection is performed using the selection constants as described in the text. The cycle time is

$t_{cycle}=t_{{SEL}_{SQRT}}+t_{buff}+t_{mux}+t_{HA}+t_{reg}=4+1+1+1+2=10t_g$

To reduce the total time, we propose to obtain all three possible values of s _j+2, corresponding to s _j+1 = −1, 0, 1, and select the correct one once s _j+1 is known, all of this in the same cycle. In other words, two result bits are generated per cycle.

(a)

Design the network for the selection of s _j+1 and s _j+2 Assume that the selection function is already implemented. Show all details; in particular, show the details of the conditional selection.

(b)

Design the network to produce the next residual (assume 8 bits in the fractional part). Show all details.

(c)

Determine the cycle time of the new scheme and compare the total time to obtain a result of 8 bits with the scheme described in the text. Discuss your findings.

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Design Full Adder Using 8 1 Mux

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